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authorColin LeMahieu <colinl@codeaurora.org>2014-12-05 20:07:19 +0000
committerColin LeMahieu <colinl@codeaurora.org>2014-12-05 20:07:19 +0000
commit19985e9a8dccc69ef66ad425d74c6dba354b88ad (patch)
tree646cdcb090d6aab440a8911405f106097085e803 /llvm/lib/Target
parent3e425c8d199bd9522824c8d648333359385e090a (diff)
downloadbcm5719-llvm-19985e9a8dccc69ef66ad425d74c6dba354b88ad.tar.gz
bcm5719-llvm-19985e9a8dccc69ef66ad425d74c6dba354b88ad.zip
[Hexagon] Adding tfrih/l instructions.
llvm-svn: 223506
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.td22
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
index aeaaf538d92..08d1d6cca8a 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -391,6 +391,28 @@ multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,
[]>;
}
+let hasSideEffects = 0, hasNewValue = 1 in
+class T_tfr16<bit isHi>
+ : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
+ "$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
+ [], "$src1 = $Rx" > {
+ bits<5> Rx;
+ bits<16> u16;
+
+ let IClass = 0b0111;
+ let Inst{27-26} = 0b00;
+ let Inst{25-24} = !if(isHi, 0b10, 0b01);
+ let Inst{23-22} = u16{15-14};
+ let Inst{21} = 0b1;
+ let Inst{20-16} = Rx;
+ let Inst{13-0} = u16{13-0};
+ }
+
+let isCodeGenOnly = 0 in {
+def A2_tfril: T_tfr16<0>;
+def A2_tfrih: T_tfr16<1>;
+}
+
multiclass ALU32_Pred<string mnemonic, RegisterClass RC, bit PredNot> {
let isPredicatedFalse = PredNot in {
defm _c#NAME : ALU32_Pbase<mnemonic, RC, PredNot, 0>;
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