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| author | Eric Christopher <echristo@gmail.com> | 2016-03-14 23:59:57 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2016-03-14 23:59:57 +0000 |
| commit | da8b3f1914e0cc4eb25af376583a23e660718115 (patch) | |
| tree | 51d9243b87c6a48708793fbd3651609d1e3cadeb /llvm/lib/Target/X86 | |
| parent | abde7dfbe9816c59795e4b94f1d1a4d7c60700f2 (diff) | |
| download | bcm5719-llvm-da8b3f1914e0cc4eb25af376583a23e660718115.tar.gz bcm5719-llvm-da8b3f1914e0cc4eb25af376583a23e660718115.zip | |
Temporarily Revert "[X86][SSE] Simplify vector LOAD + EXTEND on
pre-SSE41 hardware" as it seems to be causing crashes during code
generation in halide. PR forthcoming.
This reverts commit r263303.
llvm-svn: 263512
Diffstat (limited to 'llvm/lib/Target/X86')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index e08e26e0ecd..bf4cc0fb392 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -28585,9 +28585,7 @@ static SDValue combineToExtendVectorInReg(SDNode *N, SelectionDAG &DAG, // If target-size is 128-bits (or 256-bits on AVX2 target), then convert to // ISD::*_EXTEND_VECTOR_INREG which ensures lowering to X86ISD::V*EXT. - // Also use this if we don't have SSE41 to allow the legalizer do its job. - if (!Subtarget.hasSSE41() || VT.is128BitVector() || - (VT.is256BitVector() && Subtarget.hasInt256())) { + if (VT.is128BitVector() || (VT.is256BitVector() && Subtarget.hasInt256())) { SDValue ExOp = ExtendVecSize(DL, N0, VT.getSizeInBits()); return Opcode == ISD::SIGN_EXTEND ? DAG.getSignExtendVectorInReg(ExOp, DL, VT) |
