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| author | Craig Topper <craig.topper@intel.com> | 2018-03-29 20:41:39 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-29 20:41:39 +0000 |
| commit | 89310f56c80cbf277cd0edc8cbdda864f64c82d8 (patch) | |
| tree | ab036f31ecf23f5e4f2bd658623bd87fa09b2489 /llvm/lib/Target/X86/X86ScheduleSLM.td | |
| parent | 5c14ed89f606155089150783fc5e6ddce36c836b (diff) | |
| download | bcm5719-llvm-89310f56c80cbf277cd0edc8cbdda864f64c82d8.tar.gz bcm5719-llvm-89310f56c80cbf277cd0edc8cbdda864f64c82d8.zip | |
[X86] Correct the placement of ReadAfterLd in BEXTR and BZHI. Add dedicated SchedRW for BEXTR/BZHI.
These instructions have the memory operand before the register operand. So we need to put ReadDefault for all the load ops first. Then the ReadAfterLd
Differential Revision: https://reviews.llvm.org/D44838
llvm-svn: 328823
Diffstat (limited to 'llvm/lib/Target/X86/X86ScheduleSLM.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleSLM.td | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td index 87b1bf26c6e..64a2ec1a103 100644 --- a/llvm/lib/Target/X86/X86ScheduleSLM.td +++ b/llvm/lib/Target/X86/X86ScheduleSLM.td @@ -104,6 +104,11 @@ defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>; defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>; defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>; +// BMI1 BEXTR, BMI2 BZHI +// NOTE: These don't exist on Silvermont. Ports are guesses. +defm : SBWriteResPair<WriteBEXTR, [SLM_IEC_RSV0], 1>; +defm : SBWriteResPair<WriteBZHI, [SLM_IEC_RSV0], 1>; + // This is quite rough, latency depends on the dividend. defm : SLMWriteResPair<WriteIDiv, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; |
