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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-04 17:47:46 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-04 17:47:46 +0000 |
| commit | d7ffbc5c7e5d033ee3812fde2c13f1bb80044e70 (patch) | |
| tree | 54e65f35c8569339cc6015c72f360154121197f4 /llvm/lib/Target/X86/X86SchedHaswell.td | |
| parent | ded8ee07e991a25a27be9968340b109d8a6ff83f (diff) | |
| download | bcm5719-llvm-d7ffbc5c7e5d033ee3812fde2c13f1bb80044e70.tar.gz bcm5719-llvm-d7ffbc5c7e5d033ee3812fde2c13f1bb80044e70.zip | |
[X86] Finish splitting WriteVecShift and WriteVecIMul to remove InstRW overrides.
llvm-svn: 331543
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedHaswell.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 748f3c7ceb2..cacf24f1e34 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -205,7 +205,8 @@ defm : HWWriteResPair<WriteVecLogic, [HWPort015], 1, [1], 1, 6>; defm : HWWriteResPair<WriteVecLogicY,[HWPort015], 1, [1], 1, 7>; defm : HWWriteResPair<WriteVecALU, [HWPort15], 1, [1], 1, 6>; defm : HWWriteResPair<WriteVecALUY, [HWPort15], 1, [1], 1, 7>; -defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 6>; +defm : HWWriteResPair<WriteVecIMul, [HWPort0], 5, [1], 1, 5>; +defm : HWWriteResPair<WriteVecIMulX, [HWPort0], 5, [1], 1, 6>; defm : HWWriteResPair<WriteVecIMulY, [HWPort0], 5, [1], 1, 7>; defm : HWWriteResPair<WritePMULLD, [HWPort0], 10, [2], 2, 6>; defm : HWWriteResPair<WritePMULLDY, [HWPort0], 10, [2], 2, 7>; @@ -231,6 +232,7 @@ defm : HWWriteResPair<WriteVecShiftX, [HWPort0,HWPort5], 2, [1,1], 2, 6>; defm : X86WriteRes<WriteVecShiftY, [HWPort0,HWPort5], 4, [1,1], 2>; defm : X86WriteRes<WriteVecShiftYLd, [HWPort0,HWPort23], 8, [1,1], 2>; +defm : HWWriteResPair<WriteVecShiftImm, [HWPort0], 1, [1], 1, 5>; defm : HWWriteResPair<WriteVecShiftImmX, [HWPort0], 1, [1], 1, 6>; defm : HWWriteResPair<WriteVecShiftImmY, [HWPort0], 1, [1], 1, 7>; defm : HWWriteResPair<WriteVarVecShift, [HWPort0, HWPort5], 3, [2,1], 3, 6>; @@ -1672,14 +1674,7 @@ def HWWriteResGroup91_5 : SchedWriteRes<[HWPort0,HWPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup91_5], (instregex "MMX_PMADDUBSWrm", - "MMX_PMADDWDirm", - "MMX_PMULHRSWrm", - "MMX_PMULHUWirm", - "MMX_PMULHWirm", - "MMX_PMULLWirm", - "MMX_PMULUDQirm", - "MMX_PSADBWirm")>; +def: InstRW<[HWWriteResGroup91_5], (instregex "MMX_PSADBWirm")>; def HWWriteResGroup92_2 : SchedWriteRes<[HWPort01,HWPort23]> { let Latency = 10; |
