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| author | Sanjay Patel <spatel@rotateright.com> | 2015-08-28 14:09:48 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2015-08-28 14:09:48 +0000 |
| commit | 7c912898a518fac7d6d5922c7b0b5804f74e96f9 (patch) | |
| tree | bfa2322eba2c4d7b176adcefb4e1a6fa0c584fe1 /llvm/lib/Target/X86/X86InstrInfo.cpp | |
| parent | f36a425eba7ecea9a0c9d0cc9c7c6b43ac9bbb31 (diff) | |
| download | bcm5719-llvm-7c912898a518fac7d6d5922c7b0b5804f74e96f9.tar.gz bcm5719-llvm-7c912898a518fac7d6d5922c7b0b5804f74e96f9.zip | |
[x86] enable machine combiner reassociations for scalar 'and' insts
llvm-svn: 246300
Diffstat (limited to 'llvm/lib/Target/X86/X86InstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrInfo.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 17980e6a805..44c16a2b2f7 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -6389,10 +6389,14 @@ static bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) { // TODO: There are many more machine instruction opcodes to match: // 1. Other data types (integer, vectors) -// 2. Other math / logic operations (and, or) +// 2. Other math / logic operations (xor, or) // 3. Other forms of the same operation (intrinsics and other variants) static bool isAssociativeAndCommutative(const MachineInstr &Inst) { switch (Inst.getOpcode()) { + case X86::AND8rr: + case X86::AND16rr: + case X86::AND32rr: + case X86::AND64rr: case X86::IMUL16rr: case X86::IMUL32rr: case X86::IMUL64rr: |
