diff options
| author | Craig Topper <craig.topper@intel.com> | 2017-11-25 07:20:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-11-25 07:20:22 +0000 |
| commit | c1b3269171a2812bb699c68289c1dac980393799 (patch) | |
| tree | 0b935e2d308ec1ac2d65b2ee6fc7ac67084b727c /llvm/lib/Target/X86/X86ISelLowering.cpp | |
| parent | 5b85df8605417cdde6e7f27a4f74fac0736c92c5 (diff) | |
| download | bcm5719-llvm-c1b3269171a2812bb699c68289c1dac980393799.tar.gz bcm5719-llvm-c1b3269171a2812bb699c68289c1dac980393799.zip | |
[X86] Support folding to andnps with SSE1 only.
With SSE1 only, we emit FAND and FXOR nodes for v4f32.
llvm-svn: 318968
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 984ad373788..4db9fe8fa2b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -35033,10 +35033,13 @@ static SDValue combineFAndFNotToFAndn(SDNode *N, SelectionDAG &DAG, // Vector types are handled in combineANDXORWithAllOnesIntoANDNP(). if (!((VT == MVT::f32 && Subtarget.hasSSE1()) || - (VT == MVT::f64 && Subtarget.hasSSE2()))) + (VT == MVT::f64 && Subtarget.hasSSE2()) || + (VT == MVT::v4f32 && Subtarget.hasSSE1() && !Subtarget.hasSSE2()))) return SDValue(); auto isAllOnesConstantFP = [](SDValue V) { + if (V.getSimpleValueType().isVector()) + return ISD::isBuildVectorAllOnes(V.getNode()); auto *C = dyn_cast<ConstantFPSDNode>(V); return C && C->getConstantFPValue()->isAllOnesValue(); }; |
