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| author | Kevin Enderby <enderby@apple.com> | 2011-09-02 20:01:23 +0000 |
|---|---|---|
| committer | Kevin Enderby <enderby@apple.com> | 2011-09-02 20:01:23 +0000 |
| commit | 5b03f722926627fc8828fec3be0365ecebf9e258 (patch) | |
| tree | dbb7a8c1765b65ef819cdbd8626d6ba06df2dd30 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | aed4677a1ceab01b3cee11300795febebd54d25f (diff) | |
| download | bcm5719-llvm-5b03f722926627fc8828fec3be0365ecebf9e258.tar.gz bcm5719-llvm-5b03f722926627fc8828fec3be0365ecebf9e258.zip | |
Change X86 disassembly to print immediates values as signed by default. Special
case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 51ff5d96941..46b70b71d7e 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -28,6 +28,8 @@ #define GET_REGINFO_ENUM #include "X86GenRegisterInfo.inc" +#define GET_INSTRINFO_ENUM +#include "X86GenInstrInfo.inc" #include "X86GenEDInfo.inc" using namespace llvm; @@ -184,6 +186,38 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, break; } } + // By default sign-extend all X86 immediates based on their encoding. + else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || + type == TYPE_IMM64) { + uint32_t Opcode = mcInst.getOpcode(); + switch (operand.encoding) { + default: + break; + case ENCODING_IB: + // Special case those X86 instructions that use the imm8 as a set of + // bits, bit count, etc. and are not sign-extend. + if (Opcode != X86::BLENDPSrri && Opcode != X86::BLENDPDrri && + Opcode != X86::PBLENDWrri && Opcode != X86::MPSADBWrri && + Opcode != X86::DPPSrri && Opcode != X86::DPPDrri && + Opcode != X86::INSERTPSrr && Opcode != X86::VBLENDPSYrri && + Opcode != X86::VBLENDPSYrmi && Opcode != X86::VBLENDPDYrri && + Opcode != X86::VBLENDPDYrmi && Opcode != X86::VPBLENDWrri && + Opcode != X86::VMPSADBWrri && Opcode != X86::VDPPSYrri && + Opcode != X86::VDPPSYrmi && Opcode != X86::VDPPDrri && + Opcode != X86::VINSERTPSrr) + type = TYPE_MOFFS8; + break; + case ENCODING_IW: + type = TYPE_MOFFS16; + break; + case ENCODING_ID: + type = TYPE_MOFFS32; + break; + case ENCODING_IO: + type = TYPE_MOFFS64; + break; + } + } switch (type) { case TYPE_MOFFS8: |
