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authorJF Bastien <jfb@google.com>2015-07-01 23:41:25 +0000
committerJF Bastien <jfb@google.com>2015-07-01 23:41:25 +0000
commit03855df197944840745afd1180ebf423c7050c3c (patch)
tree10279e6f356ea28fbb0e58df4b3eb958e1471b7a /llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
parent14cd13c51313e3a53a403eeb32b091d9c6a3011c (diff)
downloadbcm5719-llvm-03855df197944840745afd1180ebf423c7050c3c.tar.gz
bcm5719-llvm-03855df197944840745afd1180ebf423c7050c3c.zip
WebAssembly: start instructions
Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
index 5e4ef9bf575..6f176194093 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h
@@ -29,7 +29,7 @@
namespace llvm {
class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
- bool HasSIMD;
+ bool HasSIMD128;
/// String name of used CPU.
std::string CPUString;
@@ -66,7 +66,8 @@ public:
bool useAA() const override { return true; }
// Predicates used by WebAssemblyInstrInfo.td.
- bool hasSIMD() const { return HasSIMD; }
+ bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
+ bool hasSIMD128() const { return HasSIMD128; }
/// Parses features string setting specified subtarget options. Definition of
/// function is auto generated by tblgen.
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