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| author | Tim Northover <tnorthover@apple.com> | 2014-04-15 13:59:49 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-15 13:59:49 +0000 |
| commit | 2f553f326ad76fbb5128afd18a3e1dc04d52dffa (patch) | |
| tree | f848982674d00ee73b6ee26938a3eabce6e0a832 /llvm/lib/Target/TargetLoweringObjectFile.cpp | |
| parent | 27010074fb25e8ac9a42f9828e3e0243c0217bdb (diff) | |
| download | bcm5719-llvm-2f553f326ad76fbb5128afd18a3e1dc04d52dffa.tar.gz bcm5719-llvm-2f553f326ad76fbb5128afd18a3e1dc04d52dffa.zip | |
FastISel: constrain the RegClass of operands when emitting instructions.
ARM64 suffered multiple -verify-machineinstr failures (principally over the
xsp/xzr issue) because FastISel was completely ignoring which subset of the
general-purpose registers each instruction required.
More fixes are coming in ARM64 specific FastISel, but this should cover the
generic problems.
llvm-svn: 206283
Diffstat (limited to 'llvm/lib/Target/TargetLoweringObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions
