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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2017-11-14 19:20:46 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2017-11-14 19:20:46 +0000
commit55b8590e03cf211563e6a7f86a48cf4c2c2ab10f (patch)
tree3ec4a01f23de8dd65ae3dda55ec51ac392a42250 /llvm/lib/Target/SystemZ
parent64e879745f2eca36bccb528e663189aee929e873 (diff)
downloadbcm5719-llvm-55b8590e03cf211563e6a7f86a48cf4c2c2ab10f.tar.gz
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[SystemZ] Fix invalid codegen using RISBMux on out-of-range bits
Before using the 32-bit RISBMux set of instructions we need to verify that the input bits are actually within range of the 32-bit instruction. This fixer PR35289. llvm-svn: 318177
Diffstat (limited to 'llvm/lib/Target/SystemZ')
-rw-r--r--llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp10
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 6ad8932caaa..802af1ae861 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -992,7 +992,15 @@ bool SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
if (Subtarget->hasMiscellaneousExtensions())
Opcode = SystemZ::RISBGN;
EVT OpcodeVT = MVT::i64;
- if (VT == MVT::i32 && Subtarget->hasHighWord()) {
+ if (VT == MVT::i32 && Subtarget->hasHighWord() &&
+ // We can only use the 32-bit instructions if all source bits are
+ // in the low 32 bits without wrapping, both after rotation (because
+ // of the smaller range for Start and End) and before rotation
+ // (because the input value is truncated).
+ RISBG.Start >= 32 && RISBG.End >= RISBG.Start &&
+ ((RISBG.Start + RISBG.Rotate) & 63) >= 32 &&
+ ((RISBG.End + RISBG.Rotate) & 63) >=
+ ((RISBG.Start + RISBG.Rotate) & 63)) {
Opcode = SystemZ::RISBMux;
OpcodeVT = MVT::i32;
RISBG.Start &= 31;
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