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authorMisha Brukman <brukman+llvm@gmail.com>2003-06-06 09:52:23 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2003-06-06 09:52:23 +0000
commit2969ec52661e8b3a878650b3ef93854dc4c46da2 (patch)
treea96f347eb3cf8eb600876ea7c9789894792759f5 /llvm/lib/Target/Sparc/SparcInstrInfo.cpp
parentf77c991d3a80e273f2df59a171857fc8646593d4 (diff)
downloadbcm5719-llvm-2969ec52661e8b3a878650b3ef93854dc4c46da2.tar.gz
bcm5719-llvm-2969ec52661e8b3a878650b3ef93854dc4c46da2.zip
* Changed Bcc instructions to behave like BPcc instructions
* BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes llvm-svn: 6655
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Sparc/SparcInstrInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
index 57ce3cd36a7..25d4627c06a 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -145,7 +145,7 @@ CreateSETSWConst(const TargetMachine& target, int32_t C,
// Sign-extend to the high 32 bits if needed.
// NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
- mvec.push_back(BuildMI(V9::SRAi6, 3).addReg(dest).addZImm(0).addRegDef(dest));
+ mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
}
@@ -692,7 +692,7 @@ CreateBitExtensionInstructions(bool signExtend,
srcVal = tmpI;
}
- mvec.push_back(BuildMI(signExtend? V9::SRAi6 : V9::SRLi6, 3)
+ mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
.addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
}
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