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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-05-20 15:02:01 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-05-20 15:02:01 +0000 |
| commit | b35efba4d9c14dce4642f3b78ac02fd2440c75ce (patch) | |
| tree | 0fd76643a398ea7a7d46ef4b2495dce9540db7b8 /llvm/lib/Target/R600/SIISelLowering.cpp | |
| parent | f41e3f56a5b337ac78816c7555add946eed725ca (diff) | |
| download | bcm5719-llvm-b35efba4d9c14dce4642f3b78ac02fd2440c75ce.tar.gz bcm5719-llvm-b35efba4d9c14dce4642f3b78ac02fd2440c75ce.zip | |
R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282
Diffstat (limited to 'llvm/lib/Target/R600/SIISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 237999f8c56..a077a95cdbb 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -513,7 +513,7 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate, } /// \brief Does "Op" fit into register class "RegClass" ? -bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op, +bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op, unsigned RegClass) const { MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); |
