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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:11:51 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:11:51 +0000 |
| commit | 676c16d08856c10e366aa67c56c1c92be737f25a (patch) | |
| tree | d3a98cff8dc24c4af038a0cb7e755242945cb86b /llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp | |
| parent | ac00f9df7933d244ab4f1078f6c4601dea6bca70 (diff) | |
| download | bcm5719-llvm-676c16d08856c10e366aa67c56c1c92be737f25a.tar.gz bcm5719-llvm-676c16d08856c10e366aa67c56c1c92be737f25a.zip | |
R600: Add IsExport bit to TableGen instruction definitions
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188516
Diffstat (limited to 'llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp index ab71bc126cc..ac3d8f63d57 100644 --- a/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp +++ b/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp @@ -373,15 +373,6 @@ public: case AMDGPU::CF_ALU: I = MI; AluClauses.push_back(MakeALUClause(MBB, I)); - case AMDGPU::EG_ExportBuf: - case AMDGPU::EG_ExportSwz: - case AMDGPU::R600_ExportBuf: - case AMDGPU::R600_ExportSwz: - case AMDGPU::RAT_WRITE_CACHELESS_32_eg: - case AMDGPU::RAT_WRITE_CACHELESS_64_eg: - case AMDGPU::RAT_WRITE_CACHELESS_128_eg: - case AMDGPU::RAT_STORE_DWORD32: - case AMDGPU::RAT_STORE_DWORD64: DEBUG(dbgs() << CfCount << ":"; MI->dump();); CfCount++; break; @@ -491,6 +482,10 @@ public: EmitALUClause(I, AluClauses[i], CfCount); } default: + if (TII->isExport(MI->getOpcode())) { + DEBUG(dbgs() << CfCount << ":"; MI->dump();); + CfCount++; + } break; } } |
