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authorTom Stellard <thomas.stellard@amd.com>2013-08-16 01:12:11 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-08-16 01:12:11 +0000
commitfbab827e2a0781ec554750ffcd4cb0f67d6bdfee (patch)
tree347488941417cd95869301c69e608d6801c6d72c /llvm/lib/Target/R600/AMDGPUISelLowering.h
parentd3ee8c103ae5fa145efa6d235f877c97967afcaa (diff)
downloadbcm5719-llvm-fbab827e2a0781ec554750ffcd4cb0f67d6bdfee.tar.gz
bcm5719-llvm-fbab827e2a0781ec554750ffcd4cb0f67d6bdfee.zip
R600: Add support for global vector stores with elements less than 32-bits
Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188520
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUISelLowering.h')
-rw-r--r--llvm/lib/Target/R600/AMDGPUISelLowering.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.h b/llvm/lib/Target/R600/AMDGPUISelLowering.h
index 8788c20903d..e3a0dcca810 100644
--- a/llvm/lib/Target/R600/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/R600/AMDGPUISelLowering.h
@@ -51,6 +51,10 @@ protected:
void AnalyzeFormalArguments(CCState &State,
const SmallVectorImpl<ISD::InputArg> &Ins) const;
+ /// \brief Lower vector stores by merging the vector elements into an integer
+ /// of the same bitwidth.
+ SDValue LowerVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
+
public:
AMDGPUTargetLowering(TargetMachine &TM);
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