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| author | Lei Huang <lei@ca.ibm.com> | 2018-04-12 18:00:14 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-04-12 18:00:14 +0000 |
| commit | 10367eb42262bdcddf171ab502a547960d509425 (patch) | |
| tree | 0b28c3647acc6030167bd45c4c70860b1104b1ed /llvm/lib/Target/PowerPC | |
| parent | 81d07fc2c19c941b2104076a18bcb118e08674b8 (diff) | |
| download | bcm5719-llvm-10367eb42262bdcddf171ab502a547960d509425.tar.gz bcm5719-llvm-10367eb42262bdcddf171ab502a547960d509425.zip | |
[Power9]Legalize and emit code for converting (Un)Signed DWord to Quad-Precision
Legalize and emit code for:
* xscvsdqp
* xscvudqp
Differential Revision: https://reviews.llvm.org/D45230
llvm-svn: 329931
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 16 |
2 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 53e77ba84e9..bde1af7e16f 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -9409,7 +9409,12 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, SDLoc(Op)); case ISD::UINT_TO_FP: - case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG); + case ISD::SINT_TO_FP: + // Conversions to f128 are legal. + if (EnableQuadPrecision && (Op->getValueType(0) == MVT::f128)) + return Op; + return LowerINT_TO_FP(Op, DAG); + case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); // Lower 64-bit shifts. diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 04a13e204ac..d84f828949e 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2512,7 +2512,12 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { // Convert (Un)Signed DWord -> QP def XSCVSDQP : X_VT5_XO5_VB5_TyVB<63, 10, 836, "xscvsdqp", vfrc, []>; + def : Pat<(f128 (sint_to_fp i64:$src)), + (f128 (XSCVSDQP (COPY_TO_REGCLASS $src, VFRC)))>; + def XSCVUDQP : X_VT5_XO5_VB5_TyVB<63, 2, 836, "xscvudqp", vfrc, []>; + def : Pat<(f128 (uint_to_fp i64:$src)), + (f128 (XSCVUDQP (COPY_TO_REGCLASS $src, VFRC)))>; let UseVSXReg = 1 in { //===--------------------------------------------------------------------===// @@ -3117,6 +3122,17 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { (COPY_TO_REGCLASS (DFLOADf32 ixaddr:$src), VSFRC)>; def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))), (f32 (DFLOADf32 ixaddr:$src))>; + + // Convert (Un)Signed DWord in memory -> QP + def : Pat<(f128 (sint_to_fp (i64 (load xaddr:$src)))), + (f128 (XSCVSDQP (LXSDX xaddr:$src)))>; + def : Pat<(f128 (sint_to_fp (i64 (load ixaddr:$src)))), + (f128 (XSCVSDQP (LXSD ixaddr:$src)))>; + def : Pat<(f128 (uint_to_fp (i64 (load xaddr:$src)))), + (f128 (XSCVUDQP (LXSDX xaddr:$src)))>; + def : Pat<(f128 (uint_to_fp (i64 (load ixaddr:$src)))), + (f128 (XSCVUDQP (LXSD ixaddr:$src)))>; + } // end HasP9Vector, AddedComplexity let Predicates = [HasP9Vector] in { |
