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| author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-12-05 20:02:22 +0000 |
|---|---|---|
| committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2014-12-05 20:02:22 +0000 |
| commit | 3e425c8d199bd9522824c8d648333359385e090a (patch) | |
| tree | 14cbb49a71e94497f1fcfb9f44e36a02d005b9bf /llvm/lib/Target/PowerPC/PPCFastISel.cpp | |
| parent | a4ab58101ac0a44af3d2260787a4bab06af38d94 (diff) | |
| download | bcm5719-llvm-3e425c8d199bd9522824c8d648333359385e090a.tar.gz bcm5719-llvm-3e425c8d199bd9522824c8d648333359385e090a.zip | |
[X86] Improved lowering of packed vector shifts to vpsllq/vpsrlq.
SSE2/AVX non-constant packed shift instructions only use the lower 64-bit of
the shift count.
This patch teaches function 'getTargetVShiftNode' how to deal with shifts
where the shift count node is of type MVT::i64.
Before this patch, function 'getTargetVShiftNode' only knew how to deal with
shift count nodes of type MVT::i32. This forced the backend to wrongly
truncate the shift count to MVT::i32, and then zero-extend it back to MVT::i64.
llvm-svn: 223505
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFastISel.cpp')
0 files changed, 0 insertions, 0 deletions
