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| author | Nate Begeman <natebegeman@mac.com> | 2005-04-06 00:25:27 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-04-06 00:25:27 +0000 |
| commit | 4164c4baac7a742f34c149ebe8bd8b38fdf49b6a (patch) | |
| tree | e82eb5a51444fa238b03f13bdd1f53b3b083bb69 /llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp | |
| parent | 20b7d2a36fe28234802e4b849745c46957967295 (diff) | |
| download | bcm5719-llvm-4164c4baac7a742f34c149ebe8bd8b38fdf49b6a.tar.gz bcm5719-llvm-4164c4baac7a742f34c149ebe8bd8b38fdf49b6a.zip | |
Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
llvm-svn: 21104
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp index 5f5ba5c0ce6..cbff20f866d 100644 --- a/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp @@ -1069,7 +1069,6 @@ unsigned ISel::SelectExpr(SDOperand N) { MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ? Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType(); bool sext = (ISD::SEXTLOAD == opcode); - bool byte = (MVT::i8 == TypeBeingLoaded); // Make sure we generate both values. if (Result != 1) |
