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| author | Diana Picus <diana.picus@linaro.org> | 2016-09-19 11:10:18 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2016-09-19 11:10:18 +0000 |
| commit | a53660e4a3d10aaba01d714a589e8f9b2f20c355 (patch) | |
| tree | a5f8f9573310003932d0c7446f47ce870b0e08b3 /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | 122d6d74f6f0abf5efd93134ef313b02cb82a792 (diff) | |
| download | bcm5719-llvm-a53660e4a3d10aaba01d714a589e8f9b2f20c355.tar.gz bcm5719-llvm-a53660e4a3d10aaba01d714a589e8f9b2f20c355.zip | |
[AArch64] Fix encoding for lsl #12 in add/sub immediates
Whenever an add/sub immediate needs a fixup, we set that immediate field to zero,
which is correct, but we also set the shift bits to zero, which is not true for
instructions that use lsl #12. This patch makes sure that if lsl #12 was used,
it will appear in the encoding of the instruction.
Differential Revision: https://reviews.llvm.org/D23930
llvm-svn: 281898
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
