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authorSimon Atanasyan <simon@atanasyan.com>2019-03-13 14:22:58 +0000
committerSimon Atanasyan <simon@atanasyan.com>2019-03-13 14:22:58 +0000
commitab45d684066eef7144f9cee9d59bd26e1fde5013 (patch)
tree0ab3d01429604e0f365ee00907b7b63aa9f86b4b /llvm/lib/Target/Mips
parent3bb5d0bb9b312f4460ad9741bea434527fe63b87 (diff)
downloadbcm5719-llvm-ab45d684066eef7144f9cee9d59bd26e1fde5013.tar.gz
bcm5719-llvm-ab45d684066eef7144f9cee9d59bd26e1fde5013.zip
[mips] Define `mov.d` instructions using `ABSS_M` multiclass. NFC
llvm-svn: 356051
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r--llvm/lib/Target/Mips/MipsInstrFPU.td7
1 files changed, 1 insertions, 6 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index f2648a7e8e4..0b03da9b5a6 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -550,12 +550,7 @@ let AdditionalPredicates = [NotInMicroMips] in {
let isMoveReg = 1 in {
def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
ABSS_FM<0x6, 16>, ISA_MIPS1;
- def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
- ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_32;
- def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
- ABSS_FM<0x6, 17>, ISA_MIPS1, FGR_64 {
- let DecoderNamespace = "MipsFP64";
- }
+ defm FMOV : ABSS_M<"mov.d", II_MOV_D>, ABSS_FM<0x6, 17>, ISA_MIPS1;
} // isMoveReg
}
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