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| author | Strahinja Petrovic <strahinja.petrovic@rt-rk.com> | 2017-08-30 11:25:38 +0000 |
|---|---|---|
| committer | Strahinja Petrovic <strahinja.petrovic@rt-rk.com> | 2017-08-30 11:25:38 +0000 |
| commit | 89df797ee978f36f66bdd2e53501aaaeea3d8c28 (patch) | |
| tree | bf9a7905659579659e13a7b31f33f63203d346b9 /llvm/lib/Target/Mips | |
| parent | b992feee1327d98070c93eabed180b7e66fba315 (diff) | |
| download | bcm5719-llvm-89df797ee978f36f66bdd2e53501aaaeea3d8c28.tar.gz bcm5719-llvm-89df797ee978f36f66bdd2e53501aaaeea3d8c28.zip | |
[MIPS] Add support to match more patterns for BBIT instruction
This patch supports one more pattern for bbit0 and bbit1
instructions, CBranchBitNum class is expanded so it can
take 32 bit immidate.
Differential Revision: https://reviews.llvm.org/D36222
llvm-svn: 312111
Diffstat (limited to 'llvm/lib/Target/Mips')
| -rw-r--r-- | llvm/lib/Target/Mips/Mips64InstrInfo.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/Mips64InstrInfo.td b/llvm/lib/Target/Mips/Mips64InstrInfo.td index ecf8f5f864f..f367ff03a96 100644 --- a/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -58,6 +58,15 @@ def PowerOf2HI : PatLeaf<(imm), [{ return false; }]>; +def PowerOf2LO_i32 : PatLeaf<(imm), [{ + if (N->getValueType(0) == MVT::i32) { + uint64_t Imm = N->getZExtValue(); + return isPowerOf2_32(Imm) && isUInt<32>(Imm); + } + else + return false; +}]>; + def assertzext_lt_i32 : PatFrag<(ops node:$src), (assertzext node:$src), [{ return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32); }]>; @@ -709,6 +718,12 @@ def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; +def : MipsPat<(brcond (i32 (seteq (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), + (BBIT0 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), + (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; +def : MipsPat<(brcond (i32 (setne (and i32:$lhs, PowerOf2LO_i32:$mask), 0)), bb:$dst), + (BBIT1 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$lhs, sub_32), + (Log2LO PowerOf2LO_i32:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS; // Atomic load patterns. def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; |
