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| author | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-02-08 09:25:17 +0000 |
|---|---|---|
| committer | Stefan Maksimovic <stefan.maksimovic@mips.com> | 2018-02-08 09:25:17 +0000 |
| commit | b3e7ed3b941b3477b7797860eb99cb5154ba015e (patch) | |
| tree | 0ad069284c49ea0e3c4cea9eeed2db247febe326 /llvm/lib/Target/Mips/MipsRegisterInfo.cpp | |
| parent | 820553fdb1e0cb49ac99a66bc5fd078283bb1a60 (diff) | |
| download | bcm5719-llvm-b3e7ed3b941b3477b7797860eb99cb5154ba015e.tar.gz bcm5719-llvm-b3e7ed3b941b3477b7797860eb99cb5154ba015e.zip | |
[mips] Define certain instructions in microMIPS32r3
Instructions affected:
mthc1, mfhc1, add.d, sub.d, mul.d, div.d,
mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d
These instructions are now defined for
microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td
since they shared their encoding with those already defined
in microMIPS32r6InstrInfo.td and have been therefore
removed from the latter file.
Some instructions present in MicroMipsInstrFPU.td which
did not have both AFGR64 and FGR64 variants defined have
been altered to do so.
Differential revision: https://reviews.llvm.org/D42738
llvm-svn: 324584
Diffstat (limited to 'llvm/lib/Target/Mips/MipsRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 0e0d82270c8..1f09ff1a6df 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -74,7 +74,9 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case Mips::GPR64RegClassID: case Mips::DSPRRegClassID: { const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); - return 28 - TFI->hasFP(MF); + bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed() + ? TFI->hasFP(MF) : true; + return 28 - HasFP; } case Mips::FGR32RegClassID: return 32; |
