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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2015-06-04 22:05:51 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2015-06-04 22:05:51 +0000 |
| commit | ff0fb6936b43d575ca23cf769bf24d9a963e6f19 (patch) | |
| tree | 8e459485d30e34d2f96e62aee9d6d1a4e2073da0 /llvm/lib/Target/Mips/MipsMachineFunction.cpp | |
| parent | d772ef3d9f8f54928043bdf4cb1518e82d254542 (diff) | |
| download | bcm5719-llvm-ff0fb6936b43d575ca23cf769bf24d9a963e6f19.tar.gz bcm5719-llvm-ff0fb6936b43d575ca23cf769bf24d9a963e6f19.zip | |
[SDAG switch lowering] Fix switch case -> or merging for 0 and INT_MIN
The big/small ordering here is based on signed values so SmallValue will
be INT_MIN and BigValue 0. This shouldn't be a problem but the code
assumed that BigValue always had more bits set than SmallValue.
We used to just miss the transformation, but a recent refactoring of
mine turned this into an assertion failure.
llvm-svn: 239105
Diffstat (limited to 'llvm/lib/Target/Mips/MipsMachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions
