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| author | Simon Dardis <simon.dardis@imgtec.com> | 2017-01-16 13:55:58 +0000 |
|---|---|---|
| committer | Simon Dardis <simon.dardis@imgtec.com> | 2017-01-16 13:55:58 +0000 |
| commit | 730fdb73a135224977901b98dd5a8dddc668084d (patch) | |
| tree | 29b0388b275643bf8b125c8ec925d65e7033c3ea /llvm/lib/Target/Mips/MCTargetDesc | |
| parent | 357f2f882795521e3522d6aa2936cfb71a0adde5 (diff) | |
| download | bcm5719-llvm-730fdb73a135224977901b98dd5a8dddc668084d.tar.gz bcm5719-llvm-730fdb73a135224977901b98dd5a8dddc668084d.zip | |
[mips] Correct c.cond.fmt instruction definition.
Permit explicit $fcc<X> operand in c.cond.fmt instruction.
Add c.cond.fmt to the MIPS to microMIPS instruction mapping table.
Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for
c.cond.fmt, bc1t, bc1f.
Reviewers: seanbruno, zoran.jovanovic, vkalintiris
Differential Revision: https://reviews.llvm.org/D24510
llvm-svn: 292117
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc')
| -rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h index 35de7b27bf1..a90db2384c4 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h @@ -123,7 +123,9 @@ namespace MipsII { HasForbiddenSlot = 1 << 5, /// IsPCRelativeLoad - A Load instruction with implicit source register /// ($pc) with explicit offset and destination register - IsPCRelativeLoad = 1 << 6 + IsPCRelativeLoad = 1 << 6, + /// HasFCCRegOperand - Instruction uses an $fcc<x> register. + HasFCCRegOperand = 1 << 7 }; } |
