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| author | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-08-22 12:17:59 +0000 |
|---|---|---|
| committer | Hrvoje Varga <Hrvoje.Varga@imgtec.com> | 2016-08-22 12:17:59 +0000 |
| commit | f0ed16eae58479155639e601bbfbff961f2cc49a (patch) | |
| tree | 90ad72b01a3a9055d126202e2dd1f41e2aaeb4de /llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | |
| parent | 80d379f228409f8d8481a265e04bcb5e082c0e74 (diff) | |
| download | bcm5719-llvm-f0ed16eae58479155639e601bbfbff961f2cc49a.tar.gz bcm5719-llvm-f0ed16eae58479155639e601bbfbff961f2cc49a.zip | |
[mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix disassembly and add operand checking to existing B<cond>C implementations
Differential Revision: https://reviews.llvm.org/D22667
llvm-svn: 279429
Diffstat (limited to 'llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp | 28 |
1 files changed, 26 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 4cc55f86a99..0614316d5ac 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -335,6 +335,30 @@ getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, return 0; } +/// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch +/// target operand. If the machine operand requires relocation, +/// record the relocation and return zero. +unsigned MipsMCCodeEmitter:: +getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + + // If the destination is an immediate, divide by 4. + if (MO.isImm()) + return MO.getImm() >> 2; + + assert(MO.isExpr() && + "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates"); + + const MCExpr *FixupExpression = MCBinaryExpr::createAdd( + MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); + Fixups.push_back(MCFixup::create(0, FixupExpression, + MCFixupKind(Mips::fixup_Mips_PC16))); + return 0; +} + /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch /// target operand. If the machine operand requires relocation, /// record the relocation and return zero. @@ -435,8 +459,8 @@ getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, const MCOperand &MO = MI.getOperand(OpNo); - // If the destination is an immediate, divide by 2. - if (MO.isImm()) return MO.getImm() >> 1; + // If the destination is an immediate, divide by 4. + if (MO.isImm()) return MO.getImm() >> 2; assert(MO.isExpr() && "getBranchTarget21OpValueMM expects only expressions or immediates"); |

