diff options
| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-05-03 20:10:36 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-05-03 20:10:36 +0000 |
| commit | 2af5037d34dd81c8ff2dcc3ee5d3f000c2ec1a01 (patch) | |
| tree | 2e6c28b27e96f5b8e21978a66a088e8b3b987eda /llvm/lib/Target/Hexagon/MCTargetDesc | |
| parent | e2ccc3fb338800134dc744091bcceaf4d3c778ce (diff) | |
| download | bcm5719-llvm-2af5037d34dd81c8ff2dcc3ee5d3f000c2ec1a01.tar.gz bcm5719-llvm-2af5037d34dd81c8ff2dcc3ee5d3f000c2ec1a01.zip | |
[Hexagon] Use automatically-generated scheduling information for HVX
Patch by Jyotsna Verma.
llvm-svn: 302073
Diffstat (limited to 'llvm/lib/Target/Hexagon/MCTargetDesc')
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp | 9 |
2 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index adb546dc214..d8009c5da08 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -29,7 +29,7 @@ namespace llvm { /// namespace HexagonII { unsigned const TypeCVI_FIRST = TypeCVI_HIST; - unsigned const TypeCVI_LAST = TypeCVI_VX_DV; + unsigned const TypeCVI_LAST = TypeCVI_VX_LATE; enum SubTarget { HasV4SubT = 0x3f, diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index a5afa1daeb9..564d43b45cb 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -102,12 +102,13 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); (*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2); (*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1); + (*TUL)[HexagonII::TypeCVI_VX_LATE] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1); (*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2); (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1); (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2); (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1); (*TUL)[HexagonII::TypeCVI_VINLANESAT] = - (CPU == "hexagonv60" || CPU == "hexagonv61" || CPU == "hexagonv61v1") + (CPU == "hexagonv60") ? UnitsAndLanes(CVI_SHIFT, 1) : UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); (*TUL)[HexagonII::TypeCVI_VM_LD] = @@ -291,10 +292,8 @@ bool HexagonShuffler::check() { break; case HexagonII::TypeNCJ: ++memory; // NV insns are memory-like. - if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) { - ++jumps, ++jump1; - foundBranches.push_back(ISJ); - } + ++jumps, ++jump1; + foundBranches.push_back(ISJ); break; case HexagonII::TypeV2LDST: if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { |
