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| author | Dorit Nuzman <dorit.nuzman@intel.com> | 2018-10-14 07:06:16 +0000 |
|---|---|---|
| committer | Dorit Nuzman <dorit.nuzman@intel.com> | 2018-10-14 07:06:16 +0000 |
| commit | 8174368955177c0765977996b00a0184921d5420 (patch) | |
| tree | 68ae87abe77ac7844dd6dae68522339840ebf075 /llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h | |
| parent | 20fa085d74336f1f5801aa53d47039adbf116a82 (diff) | |
| download | bcm5719-llvm-8174368955177c0765977996b00a0184921d5420.tar.gz bcm5719-llvm-8174368955177c0765977996b00a0184921d5420.zip | |
[IAI,LV] Add support for vectorizing predicated strided accesses using masked
interleave-group
The vectorizer currently does not attempt to create interleave-groups that
contain predicated loads/stores; predicated strided accesses can currently be
vectorized only using masked gather/scatter or scalarization. This patch makes
predicated loads/stores candidates for forming interleave-groups during the
Loop-Vectorizer's analysis, and adds the proper support for masked-interleave-
groups to the Loop-Vectorizer's planning and transformation stages. The patch
also extends the TTI API to allow querying the cost of masked interleave groups
(which each target can control); Targets that support masked vector loads/
stores may choose to enable this feature and allow vectorizing predicated
strided loads/stores using masked wide loads/stores and shuffles.
Reviewers: Ayal, hsaito, dcaballe, fhahn, javed.absar
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D53011
llvm-svn: 344472
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 2c03cd268ff..901a91692e8 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -123,7 +123,7 @@ public: bool VariableMask, unsigned Alignment); unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, - unsigned AddressSpace); + unsigned AddressSpace, bool IsMasked); unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, const Instruction *I); unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, |
