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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-15 20:16:03 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-15 20:16:03 +0000 |
commit | 6c715e1483cc2a21dd9d2076107d07b544538c89 (patch) | |
tree | 1b37dd797ae3e82dc975b4bb8e10a3a04535c68d /llvm/lib/Target/Hexagon/HexagonMachineScheduler.h | |
parent | 188d2c34e6a212650e0111116291a03479cc7e2e (diff) | |
download | bcm5719-llvm-6c715e1483cc2a21dd9d2076107d07b544538c89.tar.gz bcm5719-llvm-6c715e1483cc2a21dd9d2076107d07b544538c89.zip |
[Hexagon] Make MI scheduler check for stalls in previous packet on v60
Patch by Ikhlas Ajbar.
llvm-svn: 275606
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonMachineScheduler.h')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonMachineScheduler.h | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h index 1fe8d9d0b2c..611527eaa4c 100644 --- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h +++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -53,9 +53,13 @@ class VLIWResourceModel { unsigned TotalPackets; public: + /// Save the last formed packet. + std::vector<SUnit*> OldPacket; + +public: VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM) : SchedModel(SM), TotalPackets(0) { - ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI); + ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI); // This hard requirement could be relaxed, // but for now do not let it proceed. @@ -63,6 +67,8 @@ public: Packet.resize(SchedModel->getIssueWidth()); Packet.clear(); + OldPacket.resize(SchedModel->getIssueWidth()); + OldPacket.clear(); ResourcesModel->clearResources(); } @@ -85,7 +91,12 @@ public: bool isResourceAvailable(SUnit *SU); bool reserveResources(SUnit *SU); + void savePacket(); unsigned getTotalPackets() const { return TotalPackets; } + + bool isInPacket(SUnit *SU) const { + return std::find(Packet.begin(), Packet.end(), SU) != Packet.end(); + } }; /// Extend the standard ScheduleDAGMI to provide more context and override the @@ -99,8 +110,6 @@ public: /// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's /// time to do some work. void schedule() override; - /// Perform platform-specific DAG postprocessing. - void postprocessDAG(); }; /// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics @@ -166,6 +175,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy { void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) { DAG = dag; SchedModel = smodel; + IssueCount = 0; } bool isTop() const { |