Switch the MachineOperand accessors back to the short names like

isReg, etc., from isRegister, etc.

llvm-svn: 57006

4 files changed, 15 insertions, 16 deletions

diff --git a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 9a4102c1a46..5fb6918987c 100644
--- a/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/llvm/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -80,7 +80,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
     assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
            "Not physreg??");
     O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
-  } else if (MO.isImmediate()) {
+  } else if (MO.isImm()) {
     O << MO.getImm();
     assert(MO.getImm() < (1 << 30));
   } else {
diff --git a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
index b51440932f7..0d441146b83 100644
--- a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -148,12 +148,11 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
   unsigned rv = 0; // Return value; defaults to 0 for unhandled cases
                    // or things that get fixed up later by the JIT.
 
-  if (MO.isRegister()) {
+  if (MO.isReg()) {
     rv = getAlphaRegNumber(MO.getReg());
-  } else if (MO.isImmediate()) {
+  } else if (MO.isImm()) {
     rv = MO.getImm();
-  } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
-             || MO.isConstantPoolIndex()) {
+  } else if (MO.isGlobal() || MO.isSymbol() || MO.isCPI()) {
     DOUT << MO << " is a relocated op for " << MI << "\n";
     unsigned Reloc = 0;
     int Offset = 0;
@@ -193,19 +192,19 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI,
       assert(0 && "unknown relocatable instruction");
       abort();
     }
-    if (MO.isGlobalAddress())
+    if (MO.isGlobal())
       MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
                                                  Reloc, MO.getGlobal(), Offset,
                                                  isa<Function>(MO.getGlobal()),
                                                  useGOT));
-    else if (MO.isExternalSymbol())
+    else if (MO.isSymbol())
       MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
                                                      Reloc, MO.getSymbolName(),
                                                      Offset, true));
     else
      MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
                                           Reloc, MO.getIndex(), Offset));
-  } else if (MO.isMachineBasicBlock()) {
+  } else if (MO.isMBB()) {
     MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
                                                Alpha::reloc_bsr, MO.getMBB()));
   }else {
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index b566de45105..7f3b32f13b1 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -35,9 +35,9 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
     // or r1, r2, r2 
     // cpys(s|t) r1 r2 r2
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isReg() &&
            "invalid Alpha BIS instruction!");
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       sourceReg = MI.getOperand(1).getReg();
@@ -57,7 +57,7 @@ AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
   case Alpha::LDWU:
   case Alpha::LDS:
   case Alpha::LDT:
-    if (MI->getOperand(1).isFrameIndex()) {
+    if (MI->getOperand(1).isFI()) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -75,7 +75,7 @@ AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
   case Alpha::STW:
   case Alpha::STS:
   case Alpha::STT:
-    if (MI->getOperand(1).isFrameIndex()) {
+    if (MI->getOperand(1).isFI()) {
       FrameIndex = MI->getOperand(1).getIndex();
       return MI->getOperand(0).getReg();
     }
@@ -200,7 +200,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
     BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
     else
       MIB.addImm(MO.getImm());
@@ -245,7 +245,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
     BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
     else
       MIB.addImm(MO.getImm());
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index dd8460a0656..3523b269cf8 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -159,7 +159,7 @@ void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MachineFunction &MF = *MBB.getParent();
   bool FP = hasFP(MF);
 
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }