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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 16:47:30 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-11 16:47:30 +0000 |
| commit | 01aa56397d103e28aa577f3994f53f2f6aa82fc1 (patch) | |
| tree | a1441fff56c55f2b86f820d57e67f95ddbf16462 /llvm/lib/Target/Alpha | |
| parent | bd0127e4675e65de7154fdc6987ea0534db1e1cf (diff) | |
| download | bcm5719-llvm-01aa56397d103e28aa577f3994f53f2f6aa82fc1.tar.gz bcm5719-llvm-01aa56397d103e28aa577f3994f53f2f6aa82fc1.zip | |
continued readcyclecounter support
llvm-svn: 24300
Diffstat (limited to 'llvm/lib/Target/Alpha')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrFormats.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.td | 3 |
3 files changed, 16 insertions, 1 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index eb13486c7f2..791fcedccde 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -549,6 +549,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Node->dump(); assert(0 && "Node not handled!\n"); + case ISD::READCYCLECOUNTER: + Select(N.getOperand(0)); //Select chain + BuildMI(BB, Alpha::RPCC, 1, Result).addReg(Alpha::R31); + return Result; + case ISD::CTPOP: case ISD::CTTZ: case ISD::CTLZ: diff --git a/llvm/lib/Target/Alpha/AlphaInstrFormats.td b/llvm/lib/Target/Alpha/AlphaInstrFormats.td index c34b624dcc3..7180409ef51 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrFormats.td +++ b/llvm/lib/Target/Alpha/AlphaInstrFormats.td @@ -50,6 +50,15 @@ class MForm<bits<6> opcode, string asmstr> let Inst{20-16} = Rb; let Inst{15-0} = disp; } +class MfcForm<bits<6> opcode, bits<16> fc, string asmstr> + : InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> { + bits<5> Ra; + bits<5> Rb; + + let Inst{25-21} = Ra; + let Inst{20-16} = Rb; + let Inst{15-0} = fc; +} class MgForm<bits<6> opcode, string asmstr> : InstAlpha<opcode, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB, s16imm:$NUM), asmstr> { diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.td b/llvm/lib/Target/Alpha/AlphaInstrInfo.td index 55842964a15..e1ae7d13d5c 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.td +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.td @@ -465,6 +465,8 @@ def FBLE : FBForm<0x33, "fble $RA,$DISP">; //Floating branch if <= zero def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero +def RPCC : MfcForm<0x18, 0xC000, "rpcc $RA">; //Read process cycle counter + //Basic Floating point ops //Floats @@ -558,7 +560,6 @@ def CVTTS : FPForm<0x16, 0x7AC, "cvtts/sui $RB,$RC", //LDQ_L Mem 2B Load quadword locked //LDQ_U Mem 0B Load unaligned quadword //MB Mfc 18.4000 Memory barrier -//RPCC Mfc 18.C000 Read process cycle counter //STL_C Mem 2E Store longword conditional //STQ_C Mem 2F Store quadword conditional //STQ_U Mem 0F Store unaligned quadword |
