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| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-10-31 23:46:56 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-10-31 23:46:56 +0000 |
| commit | dfbf91e59d20b27bf7aaa411f92d07369722c009 (patch) | |
| tree | 97d2fddfd70948adc0326e225c5094c7bb090596 /llvm/lib/Target/Alpha/AlphaLLRP.cpp | |
| parent | fe43befedac43670e508682d1d9f73691600e4c4 (diff) | |
| download | bcm5719-llvm-dfbf91e59d20b27bf7aaa411f92d07369722c009.tar.gz bcm5719-llvm-dfbf91e59d20b27bf7aaa411f92d07369722c009.zip | |
more shotenning
llvm-svn: 31331
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaLLRP.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaLLRP.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaLLRP.cpp b/llvm/lib/Target/Alpha/AlphaLLRP.cpp index adae36f1cfd..eb2387740f8 100644 --- a/llvm/lib/Target/Alpha/AlphaLLRP.cpp +++ b/llvm/lib/Target/Alpha/AlphaLLRP.cpp @@ -70,7 +70,7 @@ namespace { prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; count += 1; @@ -81,9 +81,9 @@ namespace { MI->getOperand(1).getImmedValue()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; count += 2; @@ -93,11 +93,11 @@ namespace { && prev[2]->getOperand(1).getImmedValue() == MI->getOperand(1).getImmedValue()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; @@ -130,7 +130,7 @@ namespace { if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31) + BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; |
