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| author | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-10-03 15:45:36 +0000 |
| commit | 0d1e9a8e0401048b5619dd46afb744af7b028aff (patch) | |
| tree | 0b150971be1244ee265f214d4bcad572ace4128f /llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 6d8e67f512cabbd7745d4dd71b710806a8abc166 (diff) | |
| download | bcm5719-llvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.tar.gz bcm5719-llvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.zip | |
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.
llvm-svn: 57006
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp index b566de45105..7f3b32f13b1 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -35,9 +35,9 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, // or r1, r2, r2 // cpys(s|t) r1 r2 r2 assert(MI.getNumOperands() >= 3 && - MI.getOperand(0).isRegister() && - MI.getOperand(1).isRegister() && - MI.getOperand(2).isRegister() && + MI.getOperand(0).isReg() && + MI.getOperand(1).isReg() && + MI.getOperand(2).isReg() && "invalid Alpha BIS instruction!"); if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { sourceReg = MI.getOperand(1).getReg(); @@ -57,7 +57,7 @@ AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { case Alpha::LDWU: case Alpha::LDS: case Alpha::LDT: - if (MI->getOperand(1).isFrameIndex()) { + if (MI->getOperand(1).isFI()) { FrameIndex = MI->getOperand(1).getIndex(); return MI->getOperand(0).getReg(); } @@ -75,7 +75,7 @@ AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { case Alpha::STW: case Alpha::STS: case Alpha::STT: - if (MI->getOperand(1).isFrameIndex()) { + if (MI->getOperand(1).isFI()) { FrameIndex = MI->getOperand(1).getIndex(); return MI->getOperand(0).getReg(); } @@ -200,7 +200,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, BuildMI(MF, get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; - if (MO.isRegister()) + if (MO.isReg()) MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); else MIB.addImm(MO.getImm()); @@ -245,7 +245,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; - if (MO.isRegister()) + if (MO.isReg()) MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); else MIB.addImm(MO.getImm()); |
