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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-10-20 19:39:24 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-10-20 19:39:24 +0000 |
| commit | d4c0ed74e4f3d94e93fde23ccc1ce1b74d60f61f (patch) | |
| tree | 954dce81f11e249dcdcf5514b61c16454bf3fa9c /llvm/lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | 7e0e8234f67e416bd2f73a7027ff4af18e2d43be (diff) | |
| download | bcm5719-llvm-d4c0ed74e4f3d94e93fde23ccc1ce1b74d60f61f.tar.gz bcm5719-llvm-d4c0ed74e4f3d94e93fde23ccc1ce1b74d60f61f.zip | |
added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh
llvm-svn: 23849
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index bb2162b4809..e5232457254 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -697,7 +697,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Opc = opcode == ISD::CTPOP ? Alpha::CTPOP : (opcode == ISD::CTTZ ? Alpha::CTTZ : Alpha::CTLZ); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Opc, 1, Result).addReg(Alpha::R31).addReg(Tmp1); + BuildMI(BB, Opc, 1, Result).addReg(Tmp1); return Result; case ISD::MULHU: @@ -1084,10 +1084,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { break; } case MVT::i16: - BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Alpha::R31).addReg(Tmp1); + BuildMI(BB, Alpha::SEXTW, 1, Result).addReg(Tmp1); break; case MVT::i8: - BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Alpha::R31).addReg(Tmp1); + BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1); break; case MVT::i1: Tmp2 = MakeReg(MVT::i64); |
