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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-09-06 17:00:23 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-09-06 17:00:23 +0000 |
| commit | a63a066205371cf7af5febfed22150da7b1a8ad3 (patch) | |
| tree | 0bc64231f87f143eb2b47d0836d6ee13bb5d4fe1 /llvm/lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | e9e2c6d3142fbddc5f4e17083d38cadee9906b74 (diff) | |
| download | bcm5719-llvm-a63a066205371cf7af5febfed22150da7b1a8ad3.tar.gz bcm5719-llvm-a63a066205371cf7af5febfed22150da7b1a8ad3.zip | |
Fix up the AssertXext problem, as well as adding it at calls
llvm-svn: 23246
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index cc0392bdde5..8a377d056a1 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -691,10 +691,16 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { unsigned &Reg = ExprMap[N]; if (Reg) return Reg; - if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::TAILCALL) + switch(N.getOpcode()) { + default: Reg = Result = (N.getValueType() != MVT::Other) ? MakeReg(N.getValueType()) : notIn; - else { + break; + case ISD::AssertSext: + case ISD::AssertZext: + return Reg = SelectExpr(N.getOperand(0)); + case ISD::CALL: + case ISD::TAILCALL: // If this is a call instruction, make sure to prepare ALL of the result // values as well as the chain. if (Node->getNumValues() == 1) @@ -706,6 +712,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i)); ExprMap[SDOperand(Node, Node->getNumValues()-1)] = notIn; } + break; } switch (opcode) { @@ -1003,10 +1010,6 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { switch (Node->getValueType(0)) { default: Node->dump(); assert(0 && "Unknown value type for call result!"); case MVT::Other: return notIn; - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: case MVT::i64: BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R0).addReg(Alpha::R0); break; |

