massive DAGISel patch. lots and lots more stuff compiles now

llvm-svn: 24483

1 files changed, 10 insertions, 2 deletions

diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index 1e6bab6c3a9..e9e52372174 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -592,7 +592,9 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
       return Result;
     }
   case ISD::UNDEF: {
-    BuildMI(BB, Alpha::IDEF, 0, Result);
+    Opc = isFP ? (DestType == MVT::f32 ? Alpha::IDEF_F32 : Alpha::IDEF_F64) 
+      : Alpha::IDEF_I;
+    BuildMI(BB, Opc, 0, Result);
     return Result;
   }
 
@@ -1610,7 +1612,13 @@ void AlphaISel::Select(SDOperand N) {
   case ISD::ImplicitDef:
     ++count_ins;
     Select(N.getOperand(0));
-    BuildMI(BB, Alpha::IDEF, 0,
+    switch(N.getValueType()) {
+    case MVT::f32: Opc = Alpha::IDEF_F32; break;
+    case MVT::f64: Opc = Alpha::IDEF_F64; break;
+    case MVT::i64: Opc = Alpha::IDEF_I; break;
+    default: assert(0 && "should have been legalized");
+    };
+    BuildMI(BB, Opc, 0,
             cast<RegisterSDNode>(N.getOperand(1))->getReg());
     return;