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| author | Evan Cheng <evan.cheng@apple.com> | 2008-09-02 06:51:36 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-09-02 06:51:36 +0000 |
| commit | 34f3a962b028a18a622ca3604cc8ed3c76360936 (patch) | |
| tree | b7e88c46ceb78327445e40d6a2fc4df977c164d4 /llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp | |
| parent | ee29c9c2fc21dda0016343838e8730f413690a83 (diff) | |
| download | bcm5719-llvm-34f3a962b028a18a622ca3604cc8ed3c76360936.tar.gz bcm5719-llvm-34f3a962b028a18a622ca3604cc8ed3c76360936.zip | |
Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes.
llvm-svn: 55623
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp index 51a1404f32c..40e14135a40 100644 --- a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -33,7 +33,8 @@ namespace { /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr /// - int getMachineOpValue(MachineInstr &MI, MachineOperand &MO); + unsigned getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO); public: static char ID; @@ -55,7 +56,7 @@ namespace { /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. /// - unsigned getBinaryCodeForInstr(MachineInstr &MI); + unsigned getBinaryCodeForInstr(const MachineInstr &MI); private: void emitBasicBlock(MachineBasicBlock &MBB); @@ -87,7 +88,7 @@ void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { MCE.StartMachineBasicBlock(&MBB); for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { - MachineInstr &MI = *I; + const MachineInstr &MI = *I; switch(MI.getOpcode()) { default: MCE.emitWordLE(getBinaryCodeForInstr(*I)); @@ -141,10 +142,11 @@ static unsigned getAlphaRegNumber(unsigned Reg) { } } -int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { +unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO) { - int rv = 0; // Return value; defaults to 0 for unhandled cases - // or things that get fixed up later by the JIT. + unsigned rv = 0; // Return value; defaults to 0 for unhandled cases + // or things that get fixed up later by the JIT. if (MO.isRegister()) { rv = getAlphaRegNumber(MO.getReg()); |

