Fix PR 7433. Silly typo in non-Darwin ARM tail call

handling, plus correct R9 handling in that mode.

llvm-svn: 106434

2 files changed, 8 insertions, 18 deletions

diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
index c09c8a86f7f..38bb16c9ee4 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -1072,7 +1072,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
                        Pseudo, IIC_Br,
                        "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
 
-    def TCRETURNriND : AInoP<(outs), (ins tGPR:$dst, variable_ops),
+    def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
                        Pseudo, IIC_Br,
                        "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
 
@@ -1084,7 +1084,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
                    IIC_Br, "b.w\t$dst  @ TAILCALL",
                    []>, Requires<[IsThumb, IsNotDarwin]>;
 
-    def TAILJMPrND : AXI<(outs), (ins tGPR:$dst, variable_ops),
+    def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
                      BrMiscFrm, IIC_Br, "bx\t$dst  @ TAILCALL",
                    []>, Requires<[IsNotDarwin]> {
                    let Inst{7-4}   = 0b0001;
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
index e41d9fc26a7..b7e609426cb 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -386,14 +386,9 @@ def tcGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R9, R12]> {
           return ARM_GPR_NOR9_TC;
         else
           return ARM_GPR_R9_TC;
-      } else {
-        if (Subtarget.isR9Reserved())
-          return ARM_GPR_NOR9_TC;
-        else if (Subtarget.isThumb())
-          return ARM_GPR_R9_TC;
-        else
-          return ARM_GPR_R9_TC;
-      }
+      } else
+        // R9 is either callee-saved or reserved; can't use it.
+        return ARM_GPR_NOR9_TC;
     }
 
     tcGPRClass::iterator
@@ -412,14 +407,9 @@ def tcGPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R9, R12]> {
           I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
         else
           I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned));
-      } else {
-        if (Subtarget.isR9Reserved())
-          I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
-        else if (Subtarget.isThumb())
-          I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned));
-        else
-          I = ARM_GPR_R9_TC + (sizeof(ARM_GPR_R9_TC)/sizeof(unsigned));
-      }
+      } else
+        // R9 is either callee-saved or reserved; can't use it.
+        I = ARM_GPR_NOR9_TC + (sizeof(ARM_GPR_NOR9_TC)/sizeof(unsigned));
       return I;
     }
   }];