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authorSjoerd Meijer <sjoerd.meijer@arm.com>2018-08-07 15:11:47 +0000
committerSjoerd Meijer <sjoerd.meijer@arm.com>2018-08-07 15:11:47 +0000
commitb39cd886b9cd3e34f689e999f08b1f2bd2b149d7 (patch)
tree85eb363963b5a79e1d302f03679c80117a60e17b /llvm/lib/Target/ARM
parent1bfadb04995e02c657cb22219ea9702c25cdc68d (diff)
downloadbcm5719-llvm-b39cd886b9cd3e34f689e999f08b1f2bd2b149d7.tar.gz
bcm5719-llvm-b39cd886b9cd3e34f689e999f08b1f2bd2b149d7.zip
[ARM] FP16: codegen support for VACGT
Differential Revision: https://reviews.llvm.org/D50236 llvm-svn: 339148
Diffstat (limited to 'llvm/lib/Target/ARM')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrNEON.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index cff58f37ae1..5f7d22d3b1f 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -5072,7 +5072,7 @@ def VACGThd : N3VDInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
"f16", v4i16, v4f16, int_arm_neon_vacgt, 0>,
Requires<[HasNEON, HasFullFP16]>;
def VACGThq : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
- "f16", v8f16, v8f16, int_arm_neon_vacgt, 0>,
+ "f16", v8i16, v8f16, int_arm_neon_vacgt, 0>,
Requires<[HasNEON, HasFullFP16]>;
// VTST : Vector Test Bits
defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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