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| author | Mikhail Maltsev <mikhail.maltsev@arm.com> | 2019-07-31 14:22:45 +0000 |
|---|---|---|
| committer | Mikhail Maltsev <mikhail.maltsev@arm.com> | 2019-07-31 14:22:45 +0000 |
| commit | 806231ecc3964e01a439ecd4d6c38e2fa6b056d1 (patch) | |
| tree | e287ab42a36f7ebdd44d5cff5f6e8f781143b0fd /llvm/lib/Target/ARM | |
| parent | 64d7af09f53d125be4bb5af19b7f6389e3ef024e (diff) | |
| download | bcm5719-llvm-806231ecc3964e01a439ecd4d6c38e2fa6b056d1.tar.gz bcm5719-llvm-806231ecc3964e01a439ecd4d6c38e2fa6b056d1.zip | |
[ARM] Reject CSEL instructions with invalid operands
Summary:
According to the Armv8.1-M manual CSEL, CSINC, CSINV and CSNEG are
"constrained unpredictable" when SP is used as the source register Rn.
The assembler should diagnose this case.
Reviewers: momchil.velikov, dmgreen, ostannard, simon_tatham, t.p.northover
Reviewed By: ostannard
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65505
llvm-svn: 367433
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index b9691efa3e1..7e74a0a3845 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -5235,7 +5235,7 @@ def t2LoopEnd : } // end isNotDuplicable class CS<string iname, bits<4> opcode, list<dag> pattern=[]> - : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZR:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond), + : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond), AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> { bits<4> Rd; bits<4> Rm; |
