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| author | Dan Gohman <gohman@apple.com> | 2008-01-30 00:15:11 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-01-30 00:15:11 +0000 |
| commit | 47a7d6fafec81534ac060ef4be0f51e5dc892460 (patch) | |
| tree | b3117f4842098b1799268f876afc8a754b56c0ed /llvm/lib/Target/ARM | |
| parent | 162bb8060ec859324aca53d9cd0fab85812597bd (diff) | |
| download | bcm5719-llvm-47a7d6fafec81534ac060ef4be0f51e5dc892460.tar.gz bcm5719-llvm-47a7d6fafec81534ac060ef4be0f51e5dc892460.zip | |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
llvm-svn: 46538
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 9b6825d1b2d..ff299006a61 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -659,7 +659,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { case ISD::LOAD: { LoadSDNode *LD = cast<LoadSDNode>(Op); ISD::MemIndexedMode AM = LD->getAddressingMode(); - MVT::ValueType LoadedVT = LD->getLoadedVT(); + MVT::ValueType LoadedVT = LD->getMemoryVT(); if (AM != ISD::UNINDEXED) { SDOperand Offset, AMOpc; bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d62e4f473b4..a0278a4b62f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1729,11 +1729,11 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { Ptr = LD->getBasePtr(); - VT = LD->getLoadedVT(); + VT = LD->getMemoryVT(); isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { Ptr = ST->getBasePtr(); - VT = ST->getStoredVT(); + VT = ST->getMemoryVT(); } else return false; @@ -1762,10 +1762,10 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDOperand Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { - VT = LD->getLoadedVT(); + VT = LD->getMemoryVT(); isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { - VT = ST->getStoredVT(); + VT = ST->getMemoryVT(); } else return false; |

