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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-05 15:59:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-08-05 15:59:07 +0000 |
| commit | 392239296993090fd49d7a665e933ffc52e2068a (patch) | |
| tree | ed1fc454c4ac29d50ec4a980feec9855d149dfa5 /llvm/lib/Target/ARM | |
| parent | d884fbde2a829ef8c78d1a0b0f2478e7e672bc0a (diff) | |
| download | bcm5719-llvm-392239296993090fd49d7a665e933ffc52e2068a.tar.gz bcm5719-llvm-392239296993090fd49d7a665e933ffc52e2068a.zip | |
AMDGPU: Correct behavior of f16 buffer loads
Don't assume format loads for f16. Also fixes support for targets
without i16.
llvm-svn: 367879
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 7f287b41416..cce131b9bcd 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -919,9 +919,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); } - if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()){ + if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) { setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom); - setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); + if (Subtarget->hasFullFP16()) + setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); } if (!Subtarget->hasFP16()) |
