AArch64/ARM64: expunge CPSR from the sources

AArch64 does not have a CPSR register in the same way that AArch32 does. Most
of its compiler-relevant roles have been taken over by the more specific NZCV
register (representing just the flags set by normal instructions).

Its system control functions still remain, but are now under the
pseudo-register referred to as "PSTATE". They're accessed via various MRS & MSR
instructions described in the reference manual.

llvm-svn: 207645

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 3df5b8b708a..115bff89c40 100644
--- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -680,7 +680,7 @@ public:
 
     return IsKnownRegister;
   }
-  bool isSystemCPSRField() const {
+  bool isSystemPStateField() const {
     if (!isSysReg()) return false;
 
     bool IsKnownRegister;
@@ -1346,7 +1346,7 @@ public:
     Inst.addOperand(MCOperand::CreateImm(Bits));
   }
 
-  void addSystemCPSRFieldOperands(MCInst &Inst, unsigned N) const {
+  void addSystemPStateFieldOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     bool Valid;