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authorTim Northover <tnorthover@apple.com>2014-03-31 10:21:36 +0000
committerTim Northover <tnorthover@apple.com>2014-03-31 10:21:36 +0000
commit241856e5f850c1e1ba6a1e821da9a87349655b5a (patch)
tree170c6d68b5ede31b3c246ee26ae92d187285d1d0 /llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
parent9cf3d3b764043bb0a7a274b3a9f0aa2a09f2aaa1 (diff)
downloadbcm5719-llvm-241856e5f850c1e1ba6a1e821da9a87349655b5a.tar.gz
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ARM64: fix a couple of signed/unsigned comparison warnings.
llvm-svn: 205174
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp3
1 files changed, 1 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
index 4169043aa16..a3a83e1d9f9 100644
--- a/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
@@ -1308,8 +1308,7 @@ static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
} else
return false;
- assert(Shl_imm >= 0 && Shl_imm < VT.getSizeInBits() &&
- "bad amount in shift node!");
+ assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
uint64_t Srl_imm = 0;
if (!isIntImmediate(N->getOperand(1), Srl_imm))
return false;
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