diff options
| author | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
|---|---|---|
| committer | Silviu Baranga <silviu.baranga@arm.com> | 2012-03-20 15:54:56 +0000 |
| commit | 32a49333ec46ea96f973dc0b4b5a7c9f8354e47c (patch) | |
| tree | 1267a5db7ca6cacc6f19ce180f10420f2f4ae6a8 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | a95e4498040d49f2050e33756b68ac1c7d8a6a4e (diff) | |
| download | bcm5719-llvm-32a49333ec46ea96f973dc0b4b5a7c9f8354e47c.tar.gz bcm5719-llvm-32a49333ec46ea96f973dc0b4b5a7c9f8354e47c.zip | |
The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
llvm-svn: 153089
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 86f4d7b6765..e52e6c7f077 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -869,8 +869,14 @@ static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - if (RegNo == 15) return MCDisassembler::Fail; - return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); + DecodeStatus S = MCDisassembler::Success; + + if (RegNo == 15) + S = MCDisassembler::SoftFail; + + Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); + + return S; } static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo, |
