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| author | Bill Wendling <isanbard@gmail.com> | 2011-03-07 23:38:41 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2011-03-07 23:38:41 +0000 |
| commit | 77ad1dc56dcd64faa3fe718cb4133242ead2f5b0 (patch) | |
| tree | 693b845915f103d5edafd81a44bddf7df0ae092b /llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | |
| parent | 71c380f6c71da3b9d6d41e6aba43a28720171cf8 (diff) | |
| download | bcm5719-llvm-77ad1dc56dcd64faa3fe718cb4133242ead2f5b0.tar.gz bcm5719-llvm-77ad1dc56dcd64faa3fe718cb4133242ead2f5b0.zip | |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
Diffstat (limited to 'llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 32 |
1 files changed, 20 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp index 48884a1d718..10607b17c53 100644 --- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -278,12 +278,14 @@ public: unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const; - unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; + unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const; unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue) const; @@ -1209,23 +1211,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, } unsigned ARMMCCodeEmitter:: -getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const { +getShiftRight8Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { return 8 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: -getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const { +getShiftRight16Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { return 16 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: -getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl<MCFixup> &Fixups) const { +getShiftRight32Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { return 32 - MI.getOperand(Op).getImm(); } +unsigned ARMMCCodeEmitter:: +getShiftRight64Imm(const MCInst &MI, unsigned Op, + SmallVectorImpl<MCFixup> &Fixups) const { + return 64 - MI.getOperand(Op).getImm(); +} + void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { |
