[ARM][LowOverheadLoops] Allow all MVE instrs.

We have a whitelist of instructions that we allow when tail
predicating, since these are trivial ones that we've deemed need no
special handling. Now change ARMLowOverheadLoops to allow the
non-trivial instructions if they're contained within a valid VPT
block. Since a valid block is one that is predicated upon the VCTP so
we know that these non-trivial instructions will still behave as
expected once the implicit predication is used instead.

This also fixes a previous test failure.

Differential Revision: https://reviews.llvm.org/D72509

1 files changed, 18 insertions, 21 deletions

diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index dc04c541ba3..6717d4706ae 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -138,28 +138,13 @@ namespace {
       MF = ML->getHeader()->getParent();
     }
 
-    bool RecordVPTBlocks(MachineInstr *MI);
-
     // If this is an MVE instruction, check that we know how to use tail
-    // predication with it.
-    void AnalyseMVEInst(MachineInstr *MI) {
-      if (CannotTailPredicate)
-        return;
-
-      if (!RecordVPTBlocks(MI)) {
-        CannotTailPredicate = true;
-        return;
-      }
-
-      const MCInstrDesc &MCID = MI->getDesc();
-      uint64_t Flags = MCID.TSFlags;
-      if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
-        return;
+    // predication with it. Record VPT blocks and return whether the
+    // instruction is valid for tail predication.
+    bool ValidateMVEInst(MachineInstr *MI);
 
-      if ((Flags & ARMII::ValidForTailPredication) == 0) {
-        LLVM_DEBUG(dbgs() << "ARM Loops: Can't tail predicate: " << *MI);
-        CannotTailPredicate = true;
-      }
+    void AnalyseMVEInst(MachineInstr *MI) {
+      CannotTailPredicate = !ValidateMVEInst(MI);
     }
 
     bool IsTailPredicationLegal() const {
@@ -495,7 +480,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils,
              dbgs() << "ARM Loops: Couldn't validate tail predicate.\n");
 }
 
-bool LowOverheadLoop::RecordVPTBlocks(MachineInstr* MI) {
+bool LowOverheadLoop::ValidateMVEInst(MachineInstr* MI) {
   if (CannotTailPredicate)
     return false;
 
@@ -551,6 +536,18 @@ bool LowOverheadLoop::RecordVPTBlocks(MachineInstr* MI) {
     return false;
   }
 
+  uint64_t Flags = MCID.TSFlags;
+  if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+    return true;
+
+  // If we find an instruction that has been marked as not valid for tail
+  // predication, only allow the instruction if it's contained within a valid
+  // VPT block.
+  if ((Flags & ARMII::ValidForTailPredication) == 0 && !IsUse) {
+    LLVM_DEBUG(dbgs() << "ARM Loops: Can't tail predicate: " << *MI);
+    return false;
+  }
+
   return true;
 }