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| author | Eli Friedman <efriedma@quicinc.com> | 2019-08-15 23:35:53 +0000 |
|---|---|---|
| committer | Eli Friedman <efriedma@quicinc.com> | 2019-08-15 23:35:53 +0000 |
| commit | 9b9a3084521b7813ad94b5852a886a1b2c8493f0 (patch) | |
| tree | d682f6ba333967e2b6436045cf855345fd5abe13 /llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | |
| parent | b7bb9fb28f09f41e0bf26ba1a6c8c77799291deb (diff) | |
| download | bcm5719-llvm-9b9a3084521b7813ad94b5852a886a1b2c8493f0.tar.gz bcm5719-llvm-9b9a3084521b7813ad94b5852a886a1b2c8493f0.zip | |
[ARM][LowOverheadLoops] Fix generated code for "revert".
Two issues:
1. t2CMPri shouldn't use CPSR if it isn't predicated. This doesn't
really have any visible effect at the moment, but it might matter in the
future.
2. The t2CMPri generated for t2WhileLoopStart might need to use a
register that isn't LR.
My team found this because we have a patch to track register liveness
late in the pass pipeline. I'll look into upstreaming it to help catch
issues like this earlier.
Differential Revision: https://reviews.llvm.org/D66243
llvm-svn: 369069
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index c548f36d094..cfd1f408710 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -251,10 +251,10 @@ void ARMLowOverheadLoops::RevertWhile(MachineInstr *MI) const { MachineBasicBlock *MBB = MI->getParent(); MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2CMPri)); - MIB.addReg(ARM::LR); + MIB.add(MI->getOperand(0)); MIB.addImm(0); MIB.addImm(ARMCC::AL); - MIB.addReg(ARM::CPSR); + MIB.addReg(ARM::NoRegister); // TODO: Try to use tBcc instead MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc)); @@ -292,7 +292,7 @@ void ARMLowOverheadLoops::RevertLoopEnd(MachineInstr *MI) const { MIB.addReg(ARM::LR); MIB.addImm(0); MIB.addImm(ARMCC::AL); - MIB.addReg(ARM::CPSR); + MIB.addReg(ARM::NoRegister); // TODO Try to use tBcc instead. // Create bne |
