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authorDan Gohman <gohman@apple.com>2008-10-03 15:45:36 +0000
committerDan Gohman <gohman@apple.com>2008-10-03 15:45:36 +0000
commit0d1e9a8e0401048b5619dd46afb744af7b028aff (patch)
tree0b150971be1244ee265f214d4bcad572ace4128f /llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
parent6d8e67f512cabbd7745d4dd71b710806a8abc166 (diff)
downloadbcm5719-llvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.tar.gz
bcm5719-llvm-0d1e9a8e0401048b5619dd46afb744af7b028aff.zip
Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc. llvm-svn: 57006
Diffstat (limited to 'llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 8bd4caa6fd6..27fec1fc60d 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -544,13 +544,13 @@ static bool isMemoryOp(MachineInstr *MI) {
default: break;
case ARM::LDR:
case ARM::STR:
- return MI->getOperand(1).isRegister() && MI->getOperand(2).getReg() == 0;
+ return MI->getOperand(1).isReg() && MI->getOperand(2).getReg() == 0;
case ARM::FLDS:
case ARM::FSTS:
- return MI->getOperand(1).isRegister();
+ return MI->getOperand(1).isReg();
case ARM::FLDD:
case ARM::FSTD:
- return MI->getOperand(1).isRegister();
+ return MI->getOperand(1).isReg();
}
return false;
}
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