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authorRafael Espindola <rafael.espindola@gmail.com>2006-10-06 20:33:26 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2006-10-06 20:33:26 +0000
commitaa2a12f1a2fbcedef40814ac5fbc428467c2f91c (patch)
treed2bceec6cb4b433fbce47a3e55722c03061c332b /llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
parent671f25281de222d7e5fe805024d123e1420eaf28 (diff)
downloadbcm5719-llvm-aa2a12f1a2fbcedef40814ac5fbc428467c2f91c.tar.gz
bcm5719-llvm-aa2a12f1a2fbcedef40814ac5fbc428467c2f91c.zip
add optional input flag to FMRRD
llvm-svn: 30774
Diffstat (limited to 'llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index beb0d6775ad..4e417173480 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -284,8 +284,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
Ops.push_back(DAG.getRegister(Reg2, MVT::i32));
SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
- SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg}; //missing flag
- Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, 4);
+ SDOperand Ops[] = {Chain, SDReg1, SDReg2, Arg, InFlag};
+ Chain = DAG.getNode(ARMISD::FMRRD, VTs, Ops, InFlag.Val ? 5 : 4);
} else {
if (VT == MVT::f32)
Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg);
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