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| author | Chris Lattner <sabre@nondot.org> | 2010-04-07 22:58:41 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-04-07 22:58:41 +0000 |
| commit | 2104b8d36e10b07ee396dba0a6ce58e621ef88c9 (patch) | |
| tree | b2f56fa2c068df5023c81c5781bd3cebdfa371fd /llvm/lib/Target/ARM/ARMCodeEmitter.cpp | |
| parent | 4b73cfabac29092070ec658b51953a42b9eed8df (diff) | |
| download | bcm5719-llvm-2104b8d36e10b07ee396dba0a6ce58e621ef88c9.tar.gz bcm5719-llvm-2104b8d36e10b07ee396dba0a6ce58e621ef88c9.zip | |
rename llvm::llvm_report_error -> llvm::report_fatal_error
llvm-svn: 100709
Diffstat (limited to 'llvm/lib/Target/ARM/ARMCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMCodeEmitter.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp index e7aa0c86d40..32df5039f49 100644 --- a/llvm/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/llvm/lib/Target/ARM/ARMCodeEmitter.cpp @@ -559,7 +559,7 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. if (MI.getOperand(0).getSymbolName()[0]) { - llvm_report_error("JIT does not support inline asm!"); + report_fatal_error("JIT does not support inline asm!"); } break; } @@ -704,7 +704,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::BFC) { - llvm_report_error("ARMv6t2 JIT is not yet supported."); + report_fatal_error("ARMv6t2 JIT is not yet supported."); } // Part of binary is determined by TableGn. |
