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| author | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-03-14 05:01:45 +0000 |
|---|---|---|
| committer | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-03-14 05:01:45 +0000 |
| commit | f91911c3ae5f2c720a4daa171636b561cb3616a0 (patch) | |
| tree | d9ef84d23e7f9ef485fddddcd7983b3ce47c84ad /llvm/lib/Target/AMDGPU | |
| parent | d60ae33d2961937635f49583898b40e9722592d8 (diff) | |
| download | bcm5719-llvm-f91911c3ae5f2c720a4daa171636b561cb3616a0.tar.gz bcm5719-llvm-f91911c3ae5f2c720a4daa171636b561cb3616a0.zip | |
[AMDGPU] AsmParser: remove redundant isReg checks. NFC.
llvm-svn: 263407
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 66435a2f6e0..7c5cedacc8a 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -277,11 +277,11 @@ public: } bool isSCSrc32() const { - return isInlinableImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); + return isInlinableImm() || isRegClass(AMDGPU::SReg_32RegClassID); } bool isSCSrc64() const { - return isInlinableImm() || (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)); + return isInlinableImm() || isRegClass(AMDGPU::SReg_64RegClassID); } bool isSSrc32() const { @@ -295,11 +295,11 @@ public: } bool isVCSrc32() const { - return isInlinableImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID)); + return isInlinableImm() || isRegClass(AMDGPU::VS_32RegClassID); } bool isVCSrc64() const { - return isInlinableImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID)); + return isInlinableImm() || isRegClass(AMDGPU::VS_64RegClassID); } bool isVSrc32() const { @@ -1752,7 +1752,7 @@ static bool isVOP3(OperandVector &Operands) { if (Operands.size() >= 2) { AMDGPUOperand &DstOp = ((AMDGPUOperand&)*Operands[1]); - if (DstOp.isReg() && DstOp.isRegClass(AMDGPU::SGPR_64RegClassID)) + if (DstOp.isRegClass(AMDGPU::SGPR_64RegClassID)) return true; } @@ -1761,8 +1761,8 @@ static bool isVOP3(OperandVector &Operands) { if (Operands.size() > 3) { AMDGPUOperand &Src1Op = ((AMDGPUOperand&)*Operands[3]); - if (Src1Op.isReg() && (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) || - Src1Op.isRegClass(AMDGPU::SReg_64RegClassID))) + if (Src1Op.isRegClass(AMDGPU::SReg_32RegClassID) || + Src1Op.isRegClass(AMDGPU::SReg_64RegClassID)) return true; } return false; |
